Refresh-aware loop scheduling for high performance low power volatile STT-RAM.
Keni QiuJunpeng LuoZhiyao GongWeigong ZhangJing WangYuanchao XuTao LiChun Jason XuePublished in: ICCD (2016)
Keyphrases
- low power
- low power consumption
- signal processor
- power consumption
- low cost
- high speed
- scheduling problem
- single chip
- wireless transmission
- scheduling algorithm
- digital signal processing
- high power
- vlsi circuits
- real time
- logic circuits
- mixed signal
- resource constraints
- cmos technology
- low voltage
- parallel machines
- power reduction
- signal processing
- gate array
- vlsi architecture
- random access memory
- multi channel
- ultra low power