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Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor.
Maria G. Koziri
Dimitrios Zacharis
Ioannis Katsavounidis
Nikolaos Bellas
Published in:
IEEE Trans. Consumer Electron. (2011)
Keyphrases
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video decoder
single instruction multiple data
video codec
parallel processing
memory subsystem
video coding
bitstream
computer architecture
parallel architectures
parallel algorithm
instruction set
platform independent
parallel implementation
real time
video quality
efficient implementation
feature vectors