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A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.
Masayuki Miyazaki
Hiroyuki Mizuno
Koichiro Ishibashi
Published in:
ISLPED (1998)
Keyphrases
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low voltage
adaptive threshold
design considerations
cmos technology
power management
power dissipation
high speed
simulated annealing
real time
low cost
power consumption
image processing
low power