A parameterized timing-aware flip-flop merging algorithm for clock power reduction.
Chaochao FengDaheng YueZhenyu ZhaoZhuofan LiaoPublished in: DATE (2018)
Keyphrases
- merging algorithm
- power consumption
- power dissipation
- power reduction
- flip flops
- low power
- power saving
- energy efficiency
- high speed
- cmos technology
- watershed algorithm
- energy saving
- digital signal processing
- data center
- stopping criterion
- region merging
- real time
- finite state machines
- image analysis
- pattern recognition