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A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS.
Pieter Crombez
Geert Van der Plas
Michiel Steyaert
Jan Craninckx
Published in:
ESSCIRC (2009)
Keyphrases
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power consumption
nm technology
cmos technology
clock gating
low power
power management
power dissipation
high speed
power supply
power reduction
database
single chip
small size
markov processes
optimal control
clock frequency
markov chain