High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic.
Jose Carlos Garcia-MontesdeocaJuan A. Montiel-NelsonSaeid NooshabadiPublished in: DSD (2009)
Keyphrases
- low power consumption
- low power
- high speed
- low cost
- power consumption
- delay insensitive
- circuit design
- modal logic
- asynchronous circuits
- neural network
- logic programming
- input data
- integrated circuit
- random access memory
- cmos technology
- chip design
- metal oxide semiconductor
- power dissipation
- flash memory
- classical logic
- image sensor
- coarse grained
- higher level