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Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder.

Raju GannaShanky SaxenaGovind Singh Patel
Published in: J. Circuits Syst. Comput. (2022)
Keyphrases
  • image segmentation
  • square root
  • power dissipation
  • power consumption
  • graph cuts
  • computer vision
  • low power
  • floating point
  • phase locked loop