From Iterative Threshold Decoding to a Low-Power High-Speed Analog VLSI Decoder Implementation.
Werner G. TeichHeiko TeichGiuseppe OliveriPublished in: IWANN (2) (2019)
Keyphrases
- low power
- high speed
- analog vlsi
- focal plane
- low cost
- power consumption
- vlsi architecture
- cmos technology
- decoding algorithm
- signal processor
- low density parity check
- decoding process
- single chip
- ultra low power
- low power consumption
- frame rate
- logic circuits
- gate array
- power reduction
- vlsi circuits
- hardware implementation
- low complexity
- ldpc codes
- signal processing
- real time