Login / Signup
A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis.
Rajesh K. Bawa
Emmanuelle Encrenaz
Published in:
FTRTFT (1996)
Keyphrases
</>
formal model
formal verification
model checking
symbolic model checking
automated verification
model checker
formal models
bounded model checking
high level
machine translation
cross language information retrieval
program slicing
multi agent systems
hardware implementation
security properties
predicate calculus