A simplified and efficient implementation of FPGA-based turbo decoder.
S. SharmaSanjay AttriF. C. ChauhanPublished in: IPCCC (2003)
Keyphrases
- efficient implementation
- hardware implementation
- turbo codes
- error correction
- distributed video coding
- low complexity
- field programmable gate array
- channel coding
- compressed images
- hardware design
- video codec
- active set
- application specific
- decision feedback
- general purpose
- decoding process
- hardware architecture
- decoding algorithm
- image processing algorithms
- error concealment
- highly parallel