Login / Signup

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process.

Jae-Young ParkDae-Woo KimYoung-Sang SonJong-Kyu SongChang-Soo JangWon-Young Jung
Published in: IEICE Trans. Electron. (2011)
Keyphrases
  • high speed
  • circuit design
  • low power
  • information retrieval
  • image processing
  • real time
  • data sets
  • data mining
  • knowledge base
  • process model
  • power dissipation
  • vlsi circuits