A new NDA timing error detector for BPSK and QPSK with an efficient hardware implementation for ASIC-based and FPGA-based wireless receivers.
Yair LinnPublished in: ISCAS (4) (2004)
Keyphrases
- hardware implementation
- wireless communication
- wireless networks
- hardware architecture
- ofdm system
- efficient implementation
- hardware design
- computer simulation
- field programmable gate array
- signal processing
- communication networks
- communication systems
- wireless channels
- wireless sensor networks
- software implementation
- bit error rate
- image processing algorithms
- dedicated hardware
- fpga implementation
- pipeline architecture
- machine learning
- linear discriminant analysis
- mobile devices
- memory management
- orthogonal frequency division multiplexing
- parallel architecture
- fading channels
- wireless systems
- parallel algorithm
- data streams
- real time
- modulation scheme
- general purpose processors