A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC.
Su-Jin LeeCheong-Ghil KimShin-Dug KimPublished in: Asia-Pacific Computer Systems Architecture Conference (2005)
Keyphrases
- hardware architecture
- motion estimation
- video coding
- inter frame
- video compression standard
- coding efficiency
- variable block size
- rate distortion
- low complexity
- macroblock
- motion vectors
- motion compensation
- hardware implementation
- block matching motion estimation
- motion compensated
- video encoder
- video coding standard
- video compression
- computational complexity
- video sequences
- image sequences
- compression efficiency
- search range
- hardware architectures
- video codec
- motion field
- block matching
- high coding efficiency
- bit rate
- spatial domain
- motion estimator
- reference frame
- computer vision
- field programmable gate array
- parallel architecture
- intra prediction
- associative memory
- processing elements
- deblocking filter
- optical flow
- mode decision
- early termination
- artificial neural networks
- block size
- real time
- image coding
- video data
- multi agent systems