A Power and Performance Simulator for a Single-Chip Message-Passing Parallel Architecture.
Priyadarshini RamachandranCharles W. Lewis Jr.James M. Baker Jr.Published in: MSV/AMCS (2004)
Keyphrases
- message passing
- parallel architecture
- single chip
- shared memory
- low power
- power consumption
- belief propagation
- distributed memory
- low cost
- distributed systems
- parallel computing
- parallel machines
- sum product algorithm
- graphical models
- high speed
- parallel processing
- hardware implementation
- markov random field
- digital images
- image sensor
- message passing interface
- parallel algorithm
- image matching
- video camera
- parallel implementation