Timed verification of the generic architecture of a memory circuit using parametric timed automata.
Remy ChevallierEmmanuelle Encrenaz-TiphèneLaurent FribourgWeiwen XuPublished in: Formal Methods Syst. Des. (2009)
Keyphrases
- timed automata
- model checking
- reachability analysis
- temporal logic
- verification method
- formal verification
- finite state machines
- theorem prover
- high speed
- asynchronous circuits
- real time
- memory access
- associative memory
- analog vlsi
- theorem proving
- memory hierarchy
- memory management
- machine learning
- memory requirements
- management system
- memory usage
- data flow
- domain specific
- circuit design
- real time systems
- knowledge base
- logic synthesis
- software architecture