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A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS.
Ting Sun
Qi Yu
Daiguo Xu
Jing Li
Kejun Wu
Zhong Zhang
Yun Pang
Yan Wang
Ning Ning
Published in:
Microelectron. J. (2022)
Keyphrases
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delay insensitive
analog to digital converter
random access memory
asynchronous circuits
floating gate
shift register
high speed
logic programming
low cost
sar images
post processing
low power
logical operations
image processing
multi valued
modal logic
infrared
maximum likelihood
nm technology