Login / Signup
State Reordering for Low Power Combinational Logic.
Kun-Lin Tsai
Feipei Lai
Shanq-Jang Ruan
Szu-Wei Chaung
Published in:
Asia-Pacific Computer Systems Architecture Conference (2003)
Keyphrases
</>
low power
power consumption
high speed
low cost
logic circuits
single chip
high power
digital signal processing
vlsi circuits
vlsi architecture
image sensor
low power consumption
wireless transmission
hardware and software
power reduction