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A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS.
Markus Hiienkari
Jukka Teittinen
Lauri Koskinen
Matthew J. Turnquist
Mikko Kaltiokallio
Published in:
CICC (2014)
Keyphrases
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circuit design
knowledge base
random access memory
nm technology
high speed
low cost
wordnet
real time
power supply
predicate calculus
floating gate
silicon on insulator