A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits.

Preetham Lakshmikanthan Adrian Nunez

Published in: PATMOS (2006)

Keyphrases

power consumption
power dissipation
high speed
analog vlsi
chip design
delay insensitive
circuit design
vlsi circuits
cmos technology
power reduction
design methodology
low power
low cost
power management
low voltage
image sequences
power saving
asynchronous circuits
random access memory
data sets
image processing