On Optimized FPGA Implementations of the SHA-3 Candidate Groestl.
Bernhard JungkSteffen ReithJürgen ApfelbeckPublished in: IACR Cryptol. ePrint Arch. (2009)
Keyphrases
- hardware architectures
- software implementation
- high speed
- hardware implementation
- low cost
- real time image processing
- hardware design
- field programmable gate array
- hash functions
- efficient implementation
- fpga implementation
- decision trees
- hardware architecture
- computational power
- candidate generation
- single chip
- systolic array