Buffering Interconnect for Multicore Processor Designs.
Yifang LiuJiang HuWeiping ShiPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2008)
Keyphrases
- high speed
- cell processor
- memory management
- level parallelism
- high end
- memory access
- multicore processors
- parallel processing
- computation intensive
- hardware implementation
- computer architecture
- single chip
- multiprocessor systems
- highly parallel
- parallel architectures
- design space
- operating system
- computer systems
- parallel computing
- cache misses
- shared memory
- low power
- media processing