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270-to-300GHz Double-Balanced Parametric Upconverter Using Asymmetric MOS Varactors and a Power-Splitting- Transformer Hybrid in 65nm CMOS.
Zhiyu Chen
Wooyeol Choi
Kenneth K. O
Published in:
ISSCC (2021)
Keyphrases
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power consumption
clock gating
silicon on insulator
nm technology
high speed
low power
cmos technology
power reduction
power management
ibm power processor
power dissipation
low cost
power saving
metal oxide semiconductor
flip flops
floating gate
chip design
neural network
genetic algorithm