Design and Analysis of Low Power Dynamic Bus Based on RLC simulation.

Shanq-Jang Ruan Shang-Fang Tsai Yu-Ting Pai

Published in: ISVLSI (2007)

Keyphrases

low power
high speed
power consumption
single chip
low cost
logic circuits
low power consumption
vlsi architecture
digital signal processing
cmos technology
gate array
power reduction
computer simulation
high power
vlsi circuits
ultra low power