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168 Gb/s line rate real-time PAM receiver enabled by timing recovery with 8/7 oversampling in a single FPGA.
Arne Josten
Benedikt Baeuerle
Marco Eppenberger
E. Dornbierer
David Hillerkuss
Juerg Leuthold
Published in:
OFC (2017)
Keyphrases
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real time
high speed
low cost
fpga hardware
line segments
low power consumption
fpga implementation
fpga device
real time systems
pipelined architecture
dedicated hardware
hardware design
field programmable gate array
data acquisition
computer systems
general purpose
training data