Self-Timed Power Gating for Ultra-Low-Power Pipeline Circuit.

Shuji Sannomiya Kei Miyagi Keiichi Sakai Makoto Iwata Hiroaki Nishikawa

Published in: PDPTA (2009)

Keyphrases

low power
ultra low power
high speed
power consumption
logic circuits
power dissipation
power reduction
cmos technology
low cost
single chip
delay insensitive
digital signal processing
power management
low power consumption
real time
single phase
power saving
image sensor
low voltage
image compression
shift register