A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism.
Ryohei KobayashiKenji KisePublished in: IEICE Trans. Inf. Syst. (2017)
Keyphrases
- data compression
- compression algorithm
- data reduction
- compression scheme
- compression ratio
- compressed data
- field programmable gate array
- mixed data
- wavelet compression
- wavelet filters
- high quality
- arithmetic coding
- parallel implementation
- application specific
- bitstream
- multi dimensional
- video sequences
- high compression
- image processing