Abstraction and Acceleration in SMT-based Model-Checking for Array Programs
Francesco AlbertiSilvio GhilardiNatasha SharyginaPublished in: CoRR (2013)
Keyphrases
- model checking
- bounded model checking
- temporal logic
- finite state machines
- symbolic model checking
- formal verification
- finite state
- model checker
- automated verification
- temporal properties
- computation tree logic
- formal specification
- transition systems
- verification method
- reachability analysis
- epistemic logic
- timed automata
- abstract interpretation
- partial order reduction
- process algebra
- formal methods
- fixpoint
- concurrent systems
- reactive systems
- linear temporal logic
- deterministic finite automaton
- asynchronous circuits
- pspace complete
- planning domains
- coalition logic
- multi agent systems
- alternating time temporal logic
- artificial intelligence