Hardware architecture for list successive cancellation polar decoder.
Chuan ZhangXiaohu YouJin ShaPublished in: ISCAS (2014)
Keyphrases
- hardware architecture
- hardware implementation
- hardware architectures
- low complexity
- processing elements
- frequency domain
- block matching motion estimation
- associative memory
- field programmable gate array
- error concealment
- fourier transform
- signal processing
- real time
- distributed video coding
- polar coordinates
- machine learning
- neural network
- fine grained
- video codec
- low cost
- support vector
- information systems