High speed SAD architectures for variable block size motion estimation in HEVC video coding.
Purnachand NalluriLuis Nero AlvesAntonio NavarroPublished in: ICIP (2014)
Keyphrases
- video coding
- motion vectors
- high efficiency video coding
- high speed
- video codec
- motion estimation
- video compression
- motion compensation
- video coding standard
- bit rate
- motion compensated
- rate distortion
- block size
- video sequences
- search range
- variable block size
- macroblock
- video quality
- video data
- motion field
- block matching
- coding efficiency
- motion estimation algorithm
- reference frame
- intra prediction
- error concealment
- multiview video coding
- prediction error
- computational complexity
- inter frame
- motion estimator
- image sequences
- image quality
- bitstream
- bit allocation
- real time
- video coder
- temporal correlation
- data structure
- visual quality
- video conferencing