Dual Processing Engine Architecture to Speed Up Optimal Ate Pairing on FPGA Platform.
Zhongyuan HaoWei GuoJizeng WeiDazhi SunPublished in: Trustcom/BigDataSE/ISPA (2016)
Keyphrases
- reconfigurable hardware
- parallel architecture
- real time
- low cost
- hardware software
- hardware implementation
- systolic array
- field programmable gate array
- shared memory
- distributed processing
- central processor
- data acquisition
- dynamic programming
- real time image processing
- dedicated hardware
- hardware architectures
- parallel processing
- processing elements
- pipelined architecture
- functional units
- image processing
- fpga implementation
- hardware architecture
- data processing
- hardware design
- worst case
- general purpose processors
- fpga device
- distributed architecture
- fpga technology
- layered architecture
- design considerations
- video processing
- management system
- optimal solution
- web services
- neural network