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A Reduced-sp- \(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm.
Zain Shabbir
Anas Razzaq Ghumman
Shabbir Majeed Chaudhry
Published in:
Circuits Syst. Signal Process. (2016)
Keyphrases
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high frequency
computational complexity
low frequency
low frequency coefficients
machine learning
image processing
face recognition
data fusion