Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.
To-Wei ChenYu-Wen HuangTung-Chien ChenYu-Han ChenChuan-Yung TsaiLiang-Gee ChenPublished in: ISCAS (3) (2005)
Keyphrases
- high definition
- mpeg avc
- video coding
- video codec
- real time
- video coding standard
- hd video
- video communication
- motion estimation
- multimedia processing
- motion compensated
- rate control algorithm
- rate distortion
- low complexity
- video compression
- mode decision
- bit rate
- high resolution
- decoding process
- multiview video coding
- motion vectors
- video coder
- compression efficiency
- rate control
- macroblock
- video quality
- motion compensation
- video decoder
- distributed video coding
- inter frame
- coding efficiency
- error resilience
- computational complexity