Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding.
Amlan GangulyPartha Pratim PandeBenjamin BelzerCristian GrecuPublished in: J. Electron. Test. (2008)
Keyphrases
- low power
- error correction
- single chip
- low power consumption
- high speed
- low cost
- cmos technology
- power consumption
- mixed signal
- power dissipation
- vlsi architecture
- low density parity check
- logic circuits
- gate array
- error control
- error correcting
- nm technology
- power reduction
- ultra low power
- error detection and correction
- ldpc codes
- image sensor
- vlsi implementation
- digital signal processing
- cmos image sensor
- block codes
- signal processor
- real time
- multi channel