Bounded Depth Circuits with Weighted Symmetric Gates: Satisfiability, Lower Bounds and Compression.
Takayuki SakaiKazuhisa SetoSuguru TamakiJunichi TeruyamaPublished in: Electron. Colloquium Comput. Complex. (2016)
Keyphrases
- lower bound
- logic circuits
- upper bound
- depth information
- satisfiability problem
- branch and bound algorithm
- np hard
- data compression
- propositional logic
- image compression
- compression algorithm
- objective function
- branch and bound
- depth map
- np complete
- worst case
- compression ratio
- compression scheme
- lower and upper bounds
- quadratic assignment problem
- truth table
- upper and lower bounds
- max sat
- circuit design
- high speed
- computational complexity
- delay insensitive
- optimal solution