Gated clock routing for low-power microprocessor design.
Jaewon OhMassoud PedramPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2001)
Keyphrases
- low power
- high speed
- power consumption
- single chip
- logic circuits
- vlsi architecture
- low cost
- low power consumption
- power dissipation
- digital signal processing
- high power
- design methodology
- gate array
- design process
- power reduction
- cmos technology
- real time
- circuit design
- vlsi circuits
- image processing
- mixed signal
- wireless transmission