Live Demo: Memory-Efficient Hardware Design for a Real-Time Convolutional Encoder-Decoder Network.

Min-Wu Jeong Chan-Yong Shin Chae-Eun Rhee

Published in: AICAS (2022)

Keyphrases

memory efficient
hardware design
real time
fpga hardware
low complexity
video codec
distributed video coding
hardware implementation
decoding process
network architecture
machine learning
motion estimation
rate distortion
integral image
successive approximation
video coding