Clusteringverfahren zur effektiven Nutzung der Logikressourcen hierarchischer FPGA-Architekturen.
Valerij MatrosePublished in: MBMV (2007)
Keyphrases
- hardware implementation
- field programmable gate array
- high speed
- real time image processing
- verilog hdl
- low cost
- real time
- hardware design
- fpga implementation
- signal processing
- hardware architecture
- image processing
- systolic array
- massively parallel
- artificial intelligence
- programmable logic
- hardware architectures
- pipelined architecture
- fpga hardware
- genetic algorithm