Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators.
Jeff ZhangZahra GhodsiSiddharth GargKartheek RangineniPublished in: IEEE Des. Test (2020)
Keyphrases
- low power
- deep learning
- error resilience
- systolic array
- ibm power processor
- power consumption
- low cost
- error propagation
- high speed
- power management
- data flow
- unsupervised learning
- video coding
- parallel architecture
- packet loss
- bitstream
- distributed video coding
- video transmission
- machine learning
- video quality
- error concealment
- coding scheme
- low density parity check
- compressed video
- channel coding
- image quality
- unequal error protection
- video codec
- wireless channels
- video compression
- transform domain
- parallel implementation
- frame rate
- motion estimation
- real time