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Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs.

Giovanni BrignoneM. Usman JamalMihai T. LazarescuLuciano Lavagno
Published in: IEEE Access (2022)
Keyphrases
  • memory usage
  • learning algorithm
  • limited memory
  • recently developed
  • memory requirements
  • search space
  • higher order
  • data management
  • high level synthesis