A Formal Model for SDL Specifications Based on Timed Rewriting Logic.
L. J. StegglesPiotr KosiuczenkoPublished in: Autom. Softw. Eng. (2000)
Keyphrases
- formal model
- delay insensitive
- predicate calculus
- asynchronous circuits
- bounded model checking
- probabilistic knowledge
- formal language
- formal models
- petri net
- transition systems
- recursive programs
- rewrite rules
- model checking
- security properties
- modal logic
- high level
- operational semantics
- model checker
- formal verification
- formal specification
- timed automata
- logic programming
- query rewriting
- finite state machines
- security patterns