High efficiency and low power multi-rate LDPC decoder design for CMMB.

Xiaobo Jiang Hongyuan Li

Published in: ASICON (2011)

Keyphrases

low power
high efficiency
low density parity check
low cost
single chip
low power consumption
vlsi architecture
high speed
power consumption
logic circuits
power reduction
cmos technology
gate array
high accuracy
digital signal processing
design process
power dissipation
mixed signal
vlsi circuits
real time