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Secure Design Flow for Asynchronous Multi-valued Logic Circuits.

Ashur RafievJulian P. MurphyAlexandre Yakovlev
Published in: ISMVL (2010)
Keyphrases
  • multi valued
  • logic circuits
  • logic synthesis
  • low power
  • functional decomposition
  • motion estimation
  • case study
  • lower bound
  • high speed
  • design process
  • parallel algorithm
  • boolean functions