Massively Parallel Wireless Reconfigurable Processor Architecture and Programming.
Konstantinos SarrigeorgidisJan M. RabaeyPublished in: IPDPS (2003)
Keyphrases
- massively parallel
- processing elements
- functional units
- parallel computers
- parallel architectures
- floating point unit
- systolic array
- parallel computing
- graphics processing units
- fine grained
- hardware implementation
- high performance computing
- parallel architecture
- parallel machines
- field programmable gate array
- wireless networks
- computation intensive
- data flow
- instruction set
- general purpose processors
- processing units
- parallel programming
- distributed memory
- low cost
- programming language
- hardware architecture
- general purpose
- programming environment
- computer architecture