Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture.
Kentaro KawakamiMitsuhiko KurodaHiroshi KawaguchiMasahiko YoshimotoPublished in: ASP-DAC (2007)
Keyphrases
- pipeline architecture
- video codec
- low complexity
- video coding
- video coding standard
- high definition
- memory bandwidth
- hardware implementation
- power consumption
- rate distortion
- inter frame
- motion estimation
- complexity reduction
- computational complexity
- coding method
- coding efficiency
- error concealment
- bit rate
- rate control
- bitstream
- distributed video coding
- motion compensation
- wyner ziv
- real time
- macroblock
- video compression
- video quality
- motion vectors