A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System.

Chiou-Kou Tung Yu-Cherng Hung Shao-Hui Shieh Guo-Shing Huang

Published in: DDECS (2007)

Keyphrases

low power
high speed
logic circuits
power dissipation
power consumption
low cost
single chip
vlsi circuits
image sensor
cmos technology
high power
ultra low power
real time
mixed signal
power reduction
gate array
vlsi architecture
low power consumption
frame rate
digital signal processing