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Test Methodology for Dual-rail Asynchronous Circuits.

Kuan-Yen HuangTing-Yu ShenChien-Mo James Li
Published in: DAC (2017)
Keyphrases
  • asynchronous circuits
  • delay insensitive
  • model checking
  • process algebra
  • data sets
  • high speed
  • neural network
  • low cost
  • data structure
  • artificial neural networks
  • temporal logic