Login / Signup

Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.

J. LivingBashir M. Al-Hashimi
Published in: ISCAS (1) (1999)
Keyphrases
  • digital filters
  • dedicated hardware
  • pipelined architecture
  • hardware implementation
  • feature extraction
  • programmable logic
  • hardware design
  • hardware architecture
  • high frequency
  • numerical methods
  • floating point