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Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation.
Siarhei S. Zalivaka
Alexander V. Puchkov
Vladimir P. Klybik
Alexander A. Ivaniuk
Chip-Hong Chang
Published in:
ASP-DAC (2016)
Keyphrases
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multi valued
fpga implementation
hardware implementation
single valued
boolean functions
field programmable gate array
pattern recognition
image processing algorithms
logic synthesis
signal processing
efficient implementation