Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders.
Dimitrios BalobasNikos KonofaosPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2017)
Keyphrases
- low power
- low power consumption
- logic circuits
- power reduction
- power consumption
- low cost
- single chip
- high speed
- vlsi architecture
- power dissipation
- cmos technology
- vlsi circuits
- gate array
- digital signal processing
- design process
- mixed signal
- high power
- embedded systems
- wireless transmission
- image processing
- real time