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BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors.
Keni Qiu
Yujie Zhu
Yuanchao Xu
Qirun Huo
Chun Jason Xue
Published in:
Microelectron. J. (2019)
Keyphrases
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embedded processors
memory access
main memory
multithreading
memory subsystem
memory hierarchy
parallel processing
parallel algorithm
query processing
data access
back end
parallel computing
multiprocessor systems
hit rate
access patterns
location prediction
cache management
index structure
data management